Conferences

Authors Title Conference Page Venue Date
249 Jae Yoon Lee and Seongjae Cho Design of SiC 1T DRAM Having a Quantum Well Structure 2018 IEIE Fall Conference 81 Incheon, Korea Nov. 23-24, 2018
248 Seoyeon Go, Jae Yoon Lee, Keun Heo, Jin-Hong Park, and Seongae Cho Multi-level memory device based on silicon CMOS processing 2018 IEIE Fall Conferece 79 Incheon, Korea Nov. 23-24, 2018
247 Seongjae Cho, Eunseon Yu, Jae Hwa Seo, Baegmo Son, Sangjoon Park, Won-Jun Lee, and Jongwan Jung [Invited] Design of gate-all-around (GAA) device and SiGe epitaxy Fall Conference of the Korean Society of Semiconductor & Display Technology (KSDT) 2018 34-35 Seoul, Korea Nov. 22, 2018
246 Dong Keun Lee, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Yeon-Joon Choi, Kyungho Hong, Chaesoo Kim, Sungjun Kim, Seongjae Cho, and Byung-Gook Park Scaling Effect of Ti/HfO2/Si-p+ Stacked Resistive Switching device for Neuromorphic Application International Microprocesses and Nanotechnology Conference (MNC) 2018 16P-11-105L Sapporo, Japan Nov. 13-16, 2018
245 Min-Hwi Kim, Sungmin Hwang, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Sungjun Kim, Seongjae Cho, and Byung-Gook Park Sophisticated Conductivity Control of Gradual RRAM Cross-point Array for Reinforcement Learning International Microprocesses and Nanotechnology Conference (MNC) 2018 16P-11-103L Sapporo, Japan Nov. 13-16, 2018
244 Eunseon Yu, Seongjae Cho, and Byung-Gook Park A stand-alone synaptic transistor embedding SiGe quantum well and charge-trap layer with capabilities of short- and long-term potentiation in the biological system International Microprocesses and Nanotechnology Conference (MNC) 2018 15P-7-35 Sapporo, Japan Nov. 13-16, 2018
243 Yung Hun Jung, Jae Yoon Lee, Yongbeom Cho, Seongjae Cho, Hoon Heo, and Yun Hyun Cho Light Disturbance in Photodetector Simulation for Vehicle-to-Vehicle Visible Light Communication Asia Communications and Photonics Conference (ACP) 2018 Su2A.256 Hangzhou, China Oct. 26-29, 2018
242 Eunseon Yu and Seongjae Cho A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 255-257 Austin, USA Sep. 24-26, 2018
241 Eunseon Yu, Wookyung Sun, Jae Hwa Seo, In Man Kang, Hyungsoon Shin, and Seongjae Cho A Synaptic Transistor Featuring SiGe Quantum Well and Charge-Trap Layer for Short- and Long-Term Potentiation towards Neuromorphic System Application Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM) 841-842 Tokyo, Japan Sep. 9-13, 2018
240 Yongbeom Cho, Myung-Hyun Baek, Seongjae Cho, and Byung-Gook Park Semi-Floating-Gate Synaptic Transistor (SFGST) and Its Array Architecture for Hardware-Driven Artificial Spike Neural Network (SNN) Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM) 615-616 Tokyo, Japan Sep. 9-13, 2018
239 Jae Yoon Lee, Jongmin Ha, Il Hwan Cho, and Seongjae Cho Vertical Double-Gate 1T DRAM with an Asymmetric Oxide Barrier for Significant Enhancement of Data Retention Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials (SSDM) 151-152 Tokyo, Japan Sep. 9-13, 2018
238 Yung Hun Jung, In Man Kang, and Seongjae Cho Analysis of SiGe Heterojunction Tunneling Field-Effect Transistor in the Microwave Regime through Its Small-Signal Equivalent Circuit Progress In Electromagnetics Research Symposium (PIERS) 2018 171 Toyama, Japan Aug. 1-4, 2018
237 Yongbeom Cho and Seongjae Cho Semi-Floating-Gated Charge-Trap Synaptic Device for Artificial Spike Neural Network 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 400-402 Kitakyushu, Japan Jul. 2-4, 2018
236 Jongmin Ha, Jae Yoon Lee, Myeongseon Kim, Seongjae Cho, and Il Hwan Cho Investigation and optimization of double gate MPI 1T-DRAM structure with gate induced drain leakage operation 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 229-231 Kitakyushu, Japan Jul. 2-4, 2018
235 Daewoong Kwon, Jae Yoon Lee, and Seongjae Cho A Vertical 1T DRAM with Source-Sharing Storage Pocket for Low-Power Operation 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 223-225 Kitakyushu, Japan Jul. 2-4, 2018
234 Young Jun Yoon, Bo Gyeong Kim, Min Su Cho, Jae Hwa Seo, Seongjae Cho, and In Man Kang Polycrystalline Silicon MOSFET-based Capacitorless One-Transistor Dynamic Random-Access Memory with Asymmetric Double-gate Structure 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 211-213 Kitakyushu, Japan Jul. 2-4, 2018
233 Eunseon Yu and Seongjae Cho A more energy-efficient and highly retaining 1T DRAM with SiGe quantum well 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 205-207 Kitakyushu, Japan Jul. 2-4, 2018
232 Yeon-Joon Choi, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Seongjae Cho, and Byung-Gook Park Reliability Prediction of a Wedge Structured CBRAM through Kinetic Monte Carlo Simulation 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 156-159 Kitakyushu, Japan Jul. 2-4, 2018
231 Min-Woo Kwon, Kyungchul Park, Myung-Hyun Baek, Sungmin Hwang, Tejin Jang, Junil Lee, Sungmin Hwang, Seongjae Cho, and Byung-Gook Park Fabrication of dual gate positive feedback field effect transistor co-integrated with CMOS 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 125-126 Kitakyushu, Japan Jul. 2-4, 2018
230 Min-Hwi Kim, Sungjun Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Seongjae Cho, and Byung-Gook Park Modeling the Voltage-Dependent Resistance Change Behavior of SiNx-Based Resistive Switching Memories 2018 IEIE Summer Conference 269-270 Jeju, Korea Jun. 27-29, 2018
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