Journal Publications

Authors Title Journal Vol. No. Page Date
26 Dong Seup Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jung Han Lee, Seongjae Cho, and Byung-Gook Park Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer IEICE Transactions on Electronics E93-C 5 540-545 May 2010
25 Seongjae Cho, Hee-Sauk Jhon, Jung Hoon Lee, Se Hwan Park, Hyungcheol Shin, and Byung-Gook Park Device and Circuit Co-Design Strategy for Application to Low Noise Amplifier (LNA) Based on Silicon Nanowire MOSFETs Japanese Journal of Applied Physics 49 4 04DN03-1-04DN03-7 Apr. 2010
24 Yoon Kim, Jang-Gn Yun, Seongjae Cho, and Byung-Gook Park Highly Integrated 3-dimensional NOR Flash Array with Vertical 4-bit SONOS (V4SONOS) Journal of Institute of Electronics Engineers of Korea: Semiconductor Devices 47 2 102-107 Feb. 2010
23 Seongjae Cho, Shinichi O'uchi, Kazuhiko Endo, Takashi Matsukawa, Kunihiro Sakamoto, Yongxun Liu, Byung-Gook Park, and Meishoku Masahara Minimization of Gate-Induced Drain Leakage by Controlling Gate Underlap Length for Low-Standby-Power Operation of 20-nm-Level Four-Terminal Silicon-on-Insulator Fin-Shaped Field Effect Transistor Japanese Journal of Applied Physics 49 2 024203-1-024203-5 Feb. 2010
22 Yoon Kim, Il Han Park, Seongjae Cho, Jang-Gn Tun, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Se-Hwan Park, Dong Hua Lee, Won Bo Shim, Wandong Kim, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical NOR Array Structure IEEE Transactions on Nanotechnology 9 1 70-76 Jan. 2010
21 Seongjae Cho, Won Bo Shim, Il Han Park, Yoon Kim, and Byung-Gook Park Highly Scalable 3-D NAND-NOR Hybid Dual-Bit per Cell Flash Memory Devices with Additional Cut-off Gate Journal of the Korean Physical Society 56 1 137-141 Jan. 2010
20 Gil Sung Lee, Seongjae Cho, Jang-Gn Yun, Dong Hwa Li, Doo-Hyung Kim, Yoon Kim, Se Hwan Park, Won Bo Shim, Wan Dong Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Cone-Type SONOS Flash Memory IEEE Electron Device Letters 30 12 1332-1334 Nov. 2009
19 Seongjae Cho, Il Han Park, Yoon Kim, Se Hwan Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method IEEE Transactions on Nanotechnology 8 5 595-602 Sep. 2009
18 Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, and Byung-Gook Park Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation IEICE Transactions on Electronics E92-C 5 647-652 May 2009
17 Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park 3-Dimensional Terrace NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array IEICE Transactions on Electronics E92-C 5 653-658 May 2009
16 Doo-Hyun Kim, Il Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory IEICE Transactions on Electronics E92-C 5 659-664 May 2009
15 Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, and Seongjae Cho Nanosculpture: Three-dimensional CMOS device structures for ULSI era Microelectronics Journal 40 4-5 769-772 Apr.-May 2009
14 Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL) IEICE Transactions on Electronics E92-C 5 620-626 May 2009
13 Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park A 2-Bit Recessed Channel Nonvolatile Memory Device with a Lifted Charge-Trapping Node IEEE Transactions on Nanotechnology 8 1 111-115 Jan. 2009
12 Seongjae Cho, Il Han Park, Jung Hoon Lee, Younghwan Son, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Dependence of Program Efficiency on Channel Conditions Regarding NOR-Type Flash Memory Devices Fabricated on a Silicon-on-Insulator (SOI) Substrate Journal of the Korean Physical Society 53 6 3422-3426 Dec. 2008
11 Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park Fabrication and characterization of fin SONOS flash memory with separated double-gate structure Solid-State Electronics 52 10 1498-1504 Oct. 2008
10 Seongjae Cho, Il Han Park, Jung Hoon Lee, Jong Duk Lee, and Byung-Gook Park Evaluation and Resolution for Nonideal Characteristics of Complementary Metal-Oxide-Semiconductor Devices Fabricated on Silicon-on-Insulator Japanese Journal of Applied Physics 47 6 4408-4412 Jun. 2008
9 Seongjae Cho, Il Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI) IEICE Transactions on Electronics E91-C 5 731-735 May 2008
8 Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park Characterization of 2-Bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme IEICE Transactions on Electronics E91-C 5 742-746 May 2008
7 Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park Formation of Si-Rich Silicon Nitride with Low Deposition Rate by Using LPCVD for Nanoscale Non-Volatile-Memory Application Journal of the Korean Physical Society 51 96 S229-S233 May 2008
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