Journal Publications

Authors Title Journal Vol. No. Page Date
20 Gil Sung Lee, Seongjae Cho, Jang-Gn Yun, Dong Hwa Li, Doo-Hyung Kim, Yoon Kim, Se Hwan Park, Won Bo Shim, Wan Dong Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Cone-Type SONOS Flash Memory IEEE Electron Device Letters 30 12 1332-1334 Nov. 2009
19 Seongjae Cho, Il Han Park, Yoon Kim, Se Hwan Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method IEEE Transactions on Nanotechnology 8 5 595-602 Sep. 2009
18 Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, and Byung-Gook Park Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation IEICE Transactions on Electronics E92-C 5 647-652 May 2009
17 Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park 3-Dimensional Terrace NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array IEICE Transactions on Electronics E92-C 5 653-658 May 2009
16 Doo-Hyun Kim, Il Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory IEICE Transactions on Electronics E92-C 5 659-664 May 2009
15 Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, and Seongjae Cho Nanosculpture: Three-dimensional CMOS device structures for ULSI era Microelectronics Journal 40 4-5 769-772 Apr.-May 2009
14 Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL) IEICE Transactions on Electronics E92-C 5 620-626 May 2009
13 Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park A 2-Bit Recessed Channel Nonvolatile Memory Device with a Lifted Charge-Trapping Node IEEE Transactions on Nanotechnology 8 1 111-115 Jan. 2009
12 Seongjae Cho, Il Han Park, Jung Hoon Lee, Younghwan Son, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Dependence of Program Efficiency on Channel Conditions Regarding NOR-Type Flash Memory Devices Fabricated on a Silicon-on-Insulator (SOI) Substrate Journal of the Korean Physical Society 53 6 3422-3426 Dec. 2008
11 Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park Fabrication and characterization of fin SONOS flash memory with separated double-gate structure Solid-State Electronics 52 10 1498-1504 Oct. 2008
10 Seongjae Cho, Il Han Park, Jung Hoon Lee, Jong Duk Lee, and Byung-Gook Park Evaluation and Resolution for Nonideal Characteristics of Complementary Metal-Oxide-Semiconductor Devices Fabricated on Silicon-on-Insulator Japanese Journal of Applied Physics 47 6 4408-4412 Jun. 2008
9 Seongjae Cho, Il Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI) IEICE Transactions on Electronics E91-C 5 731-735 May 2008
8 Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park Characterization of 2-Bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme IEICE Transactions on Electronics E91-C 5 742-746 May 2008
7 Jang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, and Byung-Gook Park Formation of Si-Rich Silicon Nitride with Low Deposition Rate by Using LPCVD for Nanoscale Non-Volatile-Memory Application Journal of the Korean Physical Society 51 96 S229-S233 May 2008
6 Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park Design and Simulation of Asymmetric MOSFETs IEICE Transactions on Electronics E90-C 5 978-982 May 2007
5 Hochul Lee, Youngchang Yoon, Seongjae Cho, and Hyungcheol Shin Accurate extraction of the trap depth from RTS noise data by including poly depletion effect and surface potential variation in MOSFETs IEICE Transactions on Electronics E90-C 5 968-971 May 2007
4 Seongjae Cho, Jang-Gn Yun, Il Han Park, Jung Hun Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices IEICE Transactions on Electronics E90-C 5 988-993 May 2007
3 Seongjae Cho, Il Han Park, Tae Hun Kim, Jung Hoon Lee, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Quantitative Analysis on Voltage Schemes for Reliable Operations of a Floating Gate Type Double Gate Nonvolatile Memory Cell Journal of Semiconductor Technology and Science 5 3 195-203 Sep. 2005
2 Seongjae Cho, Il Han Park, Tae Hun Kim, Jae Sung Sim, Ki-Whan Song, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park Design and Optimization of Two-Bit Double-Gate Nonvolatile Memory Cell for Highly Reliable Operations IEEE Transactions on Nanotechnology 5 3 180-185 May 2006
1 Il Han Park, Tae Hun Kim, Seongjae Cho, Jung Hoon Lee, Jong Duk Lee, and Byung-Gook Park Depletion-Enhanced Body-Isolation (DEBI) Array on SOI for Highly Scalable and Reliable NAND Flash Memories IEEE Transactions on Nanotechnology 5 3 201-204 May 2006
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